1. Field of the Invention
This invention is related to computer systems and, more particularly, to memory management within computer systems.
2. Description of the Related Art
Typically, computer systems include one or more caches to reduce the latency of a processor's access to memory. Generally, a cache may store one or more blocks, each of which is a copy of data stored at a corresponding address in the memory system of the computer system. In cases where a system includes multiple processors, or processing cores, some caches may be exclusive to particular processors, while others are shared. As is well understood, shared levels of cache for multi-core processors and multi-threaded workloads are well-understood. However, for multi-programmed workloads, shared levels of cache can leave significant opportunity for optimization. Multiple programs (e.g., one running on each core) can interact micro-architecturally, although they have no real “relation” to one-another. Each of the programs may have very different requirements on execution resources, memory resources, etc. Consequently, the behavior of one program with respect to a shared cache may negatively impact the operation of another program.
For example, assuming a system includes a shared level three (L3) cache, one processor may be running a program with “bad” cache behavior (e.g., streaming through memory), while another processor on the same chip has “good” cache behavior (e.g., has a good L3 hit rate). The bad program can completely displace the good program's data from the L3 cache without deriving any benefit from the shared L3 space (since it is streaming).
In view of the above, a method and mechanism for detecting such scenarios and de-prioritizing the bad program's data in the L3 is desired. Accordingly, effective methods and mechanisms for managing a shared cache are desired.